MC68HC908LJ12 Datasheet, PDF (348/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Input/Output (I/O) Ports
NOTE:
For those devices packaged in a 52-pin LQFP, PTB4–PTB7 are not
connected. DDRB4–DDRB7 should be set to a 1 to configure
PTB4–PTB7 as outputs.
Address: $0005
Bit 7
6
5
4
3
2
1
Read:
DDRB7
Write:
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
Reset: 0
0
0
0
0
0
0
Figure 17-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 17-7 shows
the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBx
READ PTB ($0001)
Figure 17-7. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data
latch. When DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Input/Output (I/O) Ports
Technical Data
349