MC68HC908LJ12 Datasheet, PDF (110/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Clock Generator Module (CGM)
The relationship between the VCO frequency, f_VCLK, and the
reference frequency, f_RCLK, is
f_VCLK
=
2----^P_----N---
R
(
f_RCL
K
)
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance,
choose f_RCLK to a value determined either by other module
requirements (such as modules which are clocked by CGMXCLK),
cost requirements, or ideally, as high as the specified range
allows. See Section 23. Electrical Specifications. Choose the
reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f_RCLK to
an integer divisor of f_BUSDES, and R = 1. If f_RCLK cannot meet this
requirement, use the following equation to solve for R with
practical choices of f_RCLK, and choose the f_RCLK that gives the
lowest R.
R
=
round
R_M
AX
×






f--_{V----fC--R--L--C-K--L-D--K--E----S- }
–
i
nte
ge
r



-f-^V----f^C--_R--^L--_C-^K--_L-^D--_K--^E----^S- _{}



4. Calculate N:
N
=
r
oun

d

-R----f-^×-_R---_C-f--^V-_L---^CK---^L--_×-^K----2^D---_P-^E---^S--_{}
5. Calculate and verify the adequacy of the VCO and bus
frequencies f_VCLK and f_BUS.
f_VCLK
=
2----^P_----N---
R
(
f_RCL
K
)
f_BUS
=
-^f-^V---^C--^L---^K-
2^P × 4
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
111