MC68HC908LJ12 Datasheet, PDF (280/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

Serial Peripheral Interface Module (SPI)
14.7 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high. Figure 14-8 shows the
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA: CPOL = 1:0).
WRITE TO SPDR ¹
3
8
SPTE
SPSCK
CPHA:CPOL = 1:0
MOSI
SPRF
2
5
10
MSB
B6IT
B5IT
B4IT
B3IT
B2IT
B1IT
LSB MSB
B6IT
B5IT
B4IT
B3IT
B2IT
BIT
1
LSB MSB
B6IT
B5IT
B4IT
BYTE 1
BYTE 2
BYTE 3
4
9
READ SPSCR
6
11
READ SPDR
1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
2 BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.
7
12
7 CPU READS SPDR, CLEARING SPRF BIT.
8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
Figure 14-8. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Serial Peripheral Interface Module (SPI)
Technical Data
281