MC68HC908LJ12 Datasheet, PDF (26/413 Pages) Freescale Semiconductor, Inc – 8-bit microcontroller units

List of Figures
Figure
Title
Page
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 303
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . . 307
ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 310
ADRH and ADRL in 8-Bit Truncated Mode. . . . . . . . . . . . . . . 312
ADRH and ADRL in Right Justified Mode. . . . . . . . . . . . . . . . 312
ADRH and ADRL in Left Justified Mode . . . . . . . . . . . . . . . . . 313
ADRH and ADRL in Left Justified Sign Data Mode . . . . . . . . 313
ADC Clock Control Register (ADICLK). . . . . . . . . . . . . . . . . . 314
16-1 LCD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 319
16-2 LCD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
16-3 Simplified LCD Schematic (1/3 Duty, 1/3 Bias) . . . . . . . . . . . 322
16-4 Fast Charge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
16-5 1/3 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . . 326
16-6 Static LCD Backplane Driver Waveform. . . . . . . . . . . . . . . . . 327
16-7 1/4 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . . 327
16-8 Static LCD Frontplane Driver Waveforms. . . . . . . . . . . . . . . . 328
16-9 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 329
16-10 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 330
16-11 1/4 Duty LCD Frontplane Driver Waveforms (continued) . . . . 331
16-12 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . . . 332
16-13 BP0–BP2 and FP0–FP2 Output Waveforms for
7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . 333
16-14 "f" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .334
16-15 "e" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . 334
16-16 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . . .335
16-17 LCD Clock Register (LCDCLK). . . . . . . . . . . . . . . . . . . . . . . . 337
16-18 LCD Data Registers 1–14 (LDAT1–LDAT14) . . . . . . . . . . . . . 339
17-1
17-2
17-3
17-4
17-5
17-6
17-7
I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .342
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 345
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 349
Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
List of Figures
Technical Data
27