BCM4354KKWBGT Datasheet, PDF (70/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
WLAN Host Interfaces
Section 10: WLAN Host Interfaces
SDIO v3.0
All three package options of the BCM4354 WLAN section provide support for SDIO version 3.0, including the
new UHS-I modes:
• DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
• HS: High-speed up to 50 MHz (3.3V signaling).
• SDR12: SDR up to 25 MHz (1.8V signaling).
• SDR25: SDR up to 50 MHz (1.8V signaling).
• SDR50: SDR up to 100 MHz (1.8V signaling).
• SDR104: SDR up to 208 MHz (1.8V signaling)
• DDR50: DDR up to 50 MHz (1.8V signaling).
Note: The BCM4354 is backward compatible with SDIO v2.0 host interfaces.
The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an
interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks
from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 23 on
page 119 WLAN GPIO Functions and Strapping Options.
The following three functions are supported:
• Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B)
• Function 1 Backplane Function to access the internal system-on-chip (SoC) address space
(max. BlockSize/ByteCount = 64B)
• Function 2 WLAN Function for efficient WLAN packet transfer through DMA
(max. BlockSize/ByteCount = 512B)
SDIO Pins
Table 17: SDIO Pin Descriptions
SD 4-Bit Mode
SD 1-Bit Mode
DATA0 Data line 0
DATA Data line
DATA1 Data line 1 or Interrupt IRQ Interrupt
DATA2 Data line 2 or Read Wait RW Read Wait
DATA3 Data line 3
N/C Not used
CLK
Clock
CLK Clock
CMD
Command line
CMD Command line
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 69