BCM4354KKWBGT Datasheet, PDF (49/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
PCM Interface
Short Frame Sync, Slave Mode
Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)
PCM_BCLK
PCM_SYNC
PCM_OUT
6
PCM_IN
1
4
5
2
3
9
HIGH IMPEDANCE
7
8
Table 8: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)
Ref No.
1
2
3
4
5
6
7
8
9
Characteristics
PCM bit clock frequency
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC setup
PCM_SYNC hold
PCM_OUT delay
PCM_IN setup
PCM_IN hold
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
Minimum Typical Maximum Unit
–
–
12
MHz
41
–
–
ns
41
–
–
ns
8
–
–
ns
8
–
–
ns
0
–
25
ns
8
–
–
ns
8
–
–
ns
0
–
25
ns
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 48