BCM4354KKWBGT Datasheet, PDF (10/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
Table of Contents
Operation............................................................................................................................................... 53
USB Hub and UHE Support .................................................................................................................. 54
USB Full-Speed Timing......................................................................................................................... 55
UART Interface............................................................................................................................................ 56
I²S Interface................................................................................................................................................. 58
I²S Timing.............................................................................................................................................. 59
Section 8: FM Receiver Subsystem ................................................................................. 61
FM Radio ..................................................................................................................................................... 61
Digital FM Audio Interfaces ....................................................................................................................... 61
FM Over Bluetooth ..................................................................................................................................... 61
eSCO............................................................................................................................................................ 61
Wide Band Speech Link............................................................................................................................. 62
A2DP ............................................................................................................................................................ 62
Autotune and Search Algorithms ............................................................................................................. 62
Audio Features ........................................................................................................................................... 63
RDS/RBDS................................................................................................................................................... 65
Section 9: WLAN Global Functions ................................................................................. 66
WLAN CPU and Memory Subsystem........................................................................................................ 66
One-Time Programmable Memory ............................................................................................................ 66
GPIO Interface............................................................................................................................................. 66
External Coexistence Interface ................................................................................................................. 67
UART Interface............................................................................................................................................ 68
JTAG Interface ............................................................................................................................................ 68
SPROM Interface ........................................................................................................................................ 68
SFLASH Interface ....................................................................................................................................... 68
Section 10: WLAN Host Interfaces................................................................................... 69
SDIO v3.0..................................................................................................................................................... 69
SDIO Pins.............................................................................................................................................. 69
HSIC Interface ............................................................................................................................................ 70
PCI Express Interface................................................................................................................................. 71
Transaction Layer Interface................................................................................................................... 72
Data Link Layer ..................................................................................................................................... 72
Physical Layer ....................................................................................................................................... 73
Logical Subblock ................................................................................................................................... 73
Scrambler/Descrambler......................................................................................................................... 73
8B/10B Encoder/Decoder...................................................................................................................... 73
Elastic FIFO........................................................................................................................................... 73
Electrical Subblock ................................................................................................................................ 74
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
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