BCM4354KKWBGT Datasheet, PDF (176/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
Data Timing, DDR50 Mode
Figure 45: SDIO Data Timing (DDR50 Mode)
F_PP
SDIO_CLK
DAT[3:0]
input
Invalid
t_ISU2x
t_IH2x
Data
Invalid
t_ISU2x
t_IH2x
Data
Invalid
SDIO Timing
Data
Invalid
DAT[3:0]
output
t_ODLY2x
(min)
Data
t_ODLY2x (max)
t_ODLY2x
(min)
Data
t_ODLY2x (max)
Available timing
window for card
output transition
Data
In DDR50 mode, DAT[3:0] lines are sampled on both edges of
the clock (not applicable for CMD line)
Available timing
window for host to
sample data from card
Parameter
Input CMD
Input setup time
Input hold time
Output CMD
Output delay time
Output hold time
Input DAT
Input setup time
Input hold time
Output DAT
Output delay time
Output hold time
Table 58: SDIO Bus Timing Parameters (DDR50 Mode)
Symbol
Minimum Maximum Unit Comments
t_ISU
6
t_IH
0.8
t_ODLY
–
t_OH
1.5
t_ISU2x
3
t_IH2x
0.8
t_ODLY2x
–
t_ODLY2x
1.5
–
–
13.7
–
–
–
7.5
–
ns C_CARD < 10 pF (1 Card)
ns C_CARD < 10 pF (1 Card)
ns C_CARD < 30 pF (1 Card)
ns C_CARD < 15 pF (1 Card)
ns C_CARD < 10 pF (1 Card)
ns C_CARD < 10 pF (1 Card)
ns C_CARD < 25 pF (1 Card)
ns C_CARD < 15 pF (1 Card)
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 175