BCM4354KKWBGT Datasheet, PDF (25/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
WLAN Power Management
WLAN Power Management
The BCM4354 has been designed with the stringent power consumption requirements of mobile devices in
mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell
libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM4354 integrated
RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is
leakage current only. Additionally, the BCM4354 includes an advanced WLAN power management unit (PMU)
sequencer. The PMU sequencer provides significant power savings by putting the BCM4354 into various power
management states appropriate to the current environment and activities that are being performed. The power
management unit enables and disables internal regulators, switches, and other blocks based on a computation
of the required resources and a table that describes the relationship between resources and the time needed to
enable and disable them. Power up sequences are fully programmable. Configurable, free-running counters
(running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and
power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock
speeds are used wherever possible.
The BCM4354 WLAN power states are described as follows:
• Active mode— All WLAN blocks in the BCM4354 are powered up and fully functional with active carrier
sensing and frame transmission and receiving. All required regulators are enabled and put in the most
efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.
• Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators
are powered off. All main clocks (PLL, crystal oscillator, or TCXO) are shut down to reduce active power to
the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is
necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. Logic states in
the digital core are saved and preserved into a retention memory in the always-ON domain before the
digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a
host resume through the HSIC or SDIO bus, logic states in the digital core are restored to their pre-deep-
sleep settings to avoid lengthy HW reinitialization. In Deep-sleep mode, the primary source of power
consumption is leakage current.
• Power-down mode—The BCM4354 is effectively powered off by shutting down all internal regulators. The
chip is brought out of this mode by external logic re-enabling the internal regulators.
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 24