BCM4354KKWBGT Datasheet, PDF (67/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
WLAN Global Functions
Section 9: WLAN Global Functions
WLAN CPU and Memory Subsystem
The BCM4354 WLAN section includes an integrated ARM Cortex-R4™ 32-bit processor with internal RAM and
ROM. The ARM Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and low-
cost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response
features. Delivering a performance gain of more than 30% over the ARM7TDMI® processor, the ARM Cortex-
R4 processor implements the ARM v7-R architecture with support for the Thumb^®-2 instruction set.
At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available,
outperforming 8- and 16-bit devices on MIPS/µW.
Using multiple technologies to reduce cost, the ARM Cortex-R4 offers improved memory utilization, reduced pin
overhead, and reduced silicon area. It supports independent buses for Code and Data access (ICode/DCode
and System buses), integrated sleep modes, and extensive debug features including real time trace of program
execution.
On-chip memory for the CPU includes 768 KB SRAM and 640 KB ROM.
One-Time Programmable Memory
Various hardware configuration parameters may be stored in an internal One-Time Programmable (OTP)
memory, which is read by the system software after device reset. In addition, customer-specific parameters,
including the system vendor ID and the MAC address can be stored, depending on the specific board design.
Up to 484 bytes of user-accessible OTP are available.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be
reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with
the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively
program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle.
Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is
provided with the reference board design package.
GPIO Interface
The BCM4354 has 11 general-purpose I/O (GPIO) pins in the WLAN section that can be used to connect to
various external devices.
Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either
input or output pins via the GPIO control register. In addition, the GPIO pins can be assigned to various other
functions, see Table 26: “GPIO Alternative Signal Functions,” on page 120.
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 66