BCM4354KKWBGT Datasheet, PDF (30/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
External Frequency Reference
Table 3: Crystal Oscillator and External Clock—Requirements and Performance (Cont.)
Crystal^a
External Frequency
Reference^b,c
Parameter
Conditions/Notes
Min. Typ. Max. Min. Typ. Max. Units
Drive level
Input impedance
(WRF_XTAL_IN)
WRF_XTAL_IN
Input low level
WRF_XTAL_IN
Input high level
WRF_XTAL_IN
input voltage
(see Figure 5)
Duty cycle
Phase Noise^g
(IEEE 802.11b/g)
Phase Noise^g
(IEEE 802.11a)
Phase Noise^g
(IEEE 802.11n,
2.4 GHz)
Phase Noise^g,h
(IEEE 802.11n,
5 GHz)
Phase Noise^g
(IEEE 802.11ac,
5 GHz)
External crystal must be able to 200 –
tolerate this drive level.
Resistive
–
–
Capacitive
–
–
DC-coupled digital signal
–
–
DC-coupled digital signal
–
–
AC-coupled analog signal
–
–
37.4 MHz clock
–
–
37.4 MHz clock at 10 kHz offset –
–
37.4 MHz clock at 100 kHz offset –
–
37.4 MHz clock at 10 kHz offset –
–
37.4 MHz clock at 100 kHz offset –
–
37.4 MHz clock at 10 kHz offset –
–
37.4 MHz clock at 100 kHz offset –
–
37.4 MHz clock at 10 kHz offset –
–
37.4 MHz clock at 100 kHz offset –
–
37.4 MHz clock at 10 kHz offset –
–
37.4 MHz clock at 100 kHz offset –
–
–
–
–
–
µW
–
30
7.5 –
–
0
100 –
kΩ
–
7.5 pF
–
0.2 V
–
1.0 –
1.26 V
–
400 –
1200 mV_p-p
–
40 50 60 %
–
–
–
–129 dBc/Hz
–
–
–
–136 dBc/Hz
–
–
–
–137 dBc/Hz
–
–
–
–144 dBc/Hz
–
–
–
–134 dBc/Hz
–
–
–
–141 dBc/Hz
–
–
–
–142 dBc/Hz
–
–
–
–149 dBc/Hz
–
–
–
–150 dBc/Hz
–
–
–
–157 dBc/Hz
a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT.
b. See “External Frequency Reference” on page 28 for alternate connection methods.
c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the
reference clock frequency in MHz.
d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high.
Note that 52 MHz is not an auto–detected frequency using the LPO clock.
e. The frequency step size is approximately 80 Hz resolution.
f. It is the responsibility of the equipment designer to select oscillator components that comply with these
specifications.
g. Assumes that external clock has a flat phase noise response above 100 kHz.
h. If the reference clock frequency is <35 MHz the phase noise requirements must be tightened by an additional
2 dB.
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 29