BCM4354KKWBGT Datasheet, PDF (113/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
Signal Descriptions
Table 22: WLBGA Signal Descriptions
Ball# Signal Name
RF Switch Control Lines
R7
RF_SW_CTRL_0
N8
RF_SW_CTRL_1
P9
RF_SW_CTRL_2
N7
RF_SW_CTRL_3
N5
RF_SW_CTRL_4
P7
RF_SW_CTRL_5
P5
RF_SW_CTRL_6
M8
RF_SW_CTRL_7
K12
RF_SW_CTRL_8
J11
RF_SW_CTRL_9
M12
RF_SW_CTRL_10
L9
RF_SW_CTRL_11
J9
RF_SW_CTRL_12
K10
RF_SW_CTRL_13
M10
RF_SW_CTRL_14
L8
RF_SW_CTRL_15
WLAN PCI Express Interface
D5
PCIE_CLKREQ_L
C4
PCIE_PERST_L
B1
PCIE_RDN0
C1
PCIE_RDP0
A5
PCIE_REFCLKN
A4
PCIE_REFCLKP
A3
PCIE_TDN0
A2
PCIE_TDP0
C5
PCIE_PME_L
C3
PCIE_TESTP
C2
PCIE_TESTN
Type Description
O Programmable RF switch control lines. The control
O
lines are programmable via the driver and NVRAM
file.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
OD PCIe clock request signal which indicates when the
REFCLK to the PCIe interface can be gated.
1 = the clock can be gated
0 = the clock is required
I (PU) PCIe System Reset. This input is the PCIe reset as
defined in the PCIe base specification version 1.1.
I Receiver differential pair (×1 lane)
I
I PCIE Differential Clock inputs (negative and positive).
I ^{100 MHz differential.}
O Transmitter differential pair (×1 lane)
O
OD PCI power management event output. Used to
request a change in the device or system power state.
The assertion and deassertion of this signal is
asynchronous to the PCIe reference clock. This signal
has an open-drain output structure, as per the PCI
Bus Local Bus Specification, revision 2.3.
–
PCIe test pin
–
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 112