BCM4354KKWBGT Datasheet, PDF (14/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
List of Figures
Figure 36: Port Locations (Applies to 2.4 GHz and 5 GHz) ........................................................................... 140
Figure 37: SDIO Bus Timing (Default Mode) ................................................................................................. 167
Figure 38: SDIO Bus Timing (High-Speed Mode).......................................................................................... 169
Figure 39: SDIO Clock Timing (SDR Modes) ................................................................................................ 170
Figure 40: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 171
Figure 41: SDIO Bus Output Timing (SDR Modes up to 100 MHz) ............................................................... 172
Figure 42: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)..................................................... 172
Figure 43: ∆t_OP Consideration for Variable Data Window (SDR 104 Mode) ................................................. 173
Figure 44: SDIO Clock Timing (DDR50 Mode) .............................................................................................. 174
Figure 45: SDIO Data Timing (DDR50 Mode) ............................................................................................... 175
Figure 46: WLAN = ON, Bluetooth = ON ....................................................................................................... 181
Figure 47: WLAN = OFF, Bluetooth = OFF.................................................................................................... 181
Figure 48: WLAN = ON, Bluetooth = OFF ..................................................................................................... 182
Figure 49: WLAN = OFF, Bluetooth = ON ..................................................................................................... 182
Figure 50: WLAN Boot-Up Sequence ............................................................................................................ 183
Figure 51: 192-Ball WLBGA Package Mechanical Information ..................................................................... 186
Figure 52: WLBGA Keep-Out Areas for PCB Layout (Top View, Balls Facing Down) .................................. 187
Figure 53: 395-Bump WLCSP Package ........................................................................................................ 188
Figure 54: WLCSP Keep-Out Areas for PCB Layout (Top View, Balls Facing Down)................................... 189
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
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