BCM4354KKWBGT Datasheet, PDF (181/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
Power-Up Sequence and Timing
Section 21: Power-Up Sequence and
Timing
Sequencing of Reset and Regulator Control Signals
The BCM4354 has two signals that allow the host to control power consumption by enabling or disabling the
Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are
provided to indicate proper sequencing of the signals for various operational states (see Figure 46, Figure 47
on page 181, and Figure 48 and Figure 49 on page 182). The timing values indicated are minimum required
values; longer delays are also acceptable.
Description of Control Signals
• WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON
input to control the internal BCM4354 regulators. When this pin is high, the regulators are enabled and the
WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON
and WL_REG_ON pins are low, the regulators are disabled.
• BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM4354
regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this
pin is low and WL_REG_ON is high, the BT section is in reset.
Note:
• For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay
between consecutive toggles (where both signals have been driven low). This is to allow time for
the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush
current on the order of 36 mA during the next PMU cold start.
• The reset requirements for the Bluetooth core are also applicable for the FM core. In other words,
if FM is to be used, then the Bluetooth core must be enabled.
• The BCM4354 has an internal power-on reset (POR) circuit. The device will be held in reset for a
maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least
150 ms after VDDC and VDDIO are available before initiating SDIO accesses.
• VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the
same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 180