BCM4354KKWBGT Datasheet, PDF (60/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
I²S Interface
I²S Timing
Note: Timing values specified in Table 16 are relative to high and low threshold levels.
Table 16: Timing for I²S Transmitters and Receivers
Transmitter
Receiver
Lower LImit Upper Limit Lower Limit Upper Limit
Clock Period T
Min.
T_tr
Max.
–
Min.
–
Max.
–
Min.
T_r
Max.
–
Min.
–
Max. Notes
–
a
Master Mode: Clock generated by transmitter or receiver
HIGH t_HC
LOWt_LC
0.35T_tr –
–
– 0.35T_tr –
–
–
b
0.35T_tr –
–
– 0.35T_tr –
–
–
b
Slave Mode: Clock accepted by transmitter or receiver
HIGH t_HC
LOW t_LC
Rise time t_RC
– 0.35T_tr –
–
– 0.35T_tr –
–
c
– 0.35T_tr –
–
– 0.35T_tr –
–
c
–
– 0.15T_tr –
–
–
–
–
d
Transmitter
Delay t_dtr
Hold time t_htr
–
–
–
0.8T
–
–
–
–
e
0
–
–
–
–
–
–
–
d
Receiver
Setup time t_sr
Hold time t_hr
–
–
–
–
–
0.2T_r
–
–
f
–
–
–
–
–
0
–
–
f
a. The system clock period T must be greater than T_tr and T_r because both the transmitter and receiver have to be
able to handle the data transfer rate.
b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space
ratio. For this reason, t_HC and t_LC are specified with respect to T.
c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that
they can detect the signal. So long as the minimum periods are greater than 0.35T_r, any clock that meets the
requirements can be used.
d. Because the delay (t_dtr) and the maximum transmitter speed (defined by T_tr) are related, a fast transmitter driven
by a slow clock edge can result in t_dtr not exceeding t_RC which means t_htr becomes zero or negative. Therefore,
the transmitter has to guarantee that t_htr is greater than or equal to zero, so long as the clock rise-time t_RC is not
more than t_RCmax, where t_RCmax is not less than 0.15T_tr.
e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the
clock signal and T, always giving the receiver sufficient setup time.
f. The data setup and hold time must not be less than the specified receiver setup and hold time.
Note: The time periods specified in Figure 19 and Figure 20 are defined by the transmitter speed. The
receiver specifications must match transmitter performance.
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 59