BCM4354KKWBGT Datasheet, PDF (48/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
PCM Interface
Burst PCM Mode
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty
cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to
24 MHz. This mode of operation is initiated with an HCI command from the host.
PCM Interface Timing
Short Frame Sync, Master Mode
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode)
PCM_BCLK
PCM _SYNC
PCM _OUT
5
PC M _IN
1
4
2
3
8
HIGH IMPEDANCE
6
7
Table 7: PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No.
1
2
3
4
5
6
7
8
Characteristics
PCM bit clock frequency
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
PCM_IN hold
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
Minimum Typical
–
–
41
–
41
–
0
–
0
–
8
–
8
–
0
–
Maximum Unit
12
MHz
–
ns
–
ns
25
ns
25
ns
–
ns
–
ns
25
ns
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 47