BCM4354KKWBGT Datasheet, PDF (50/192 Pages) Cypress Semiconductor – Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM4354 Data Sheet
PCM Interface
Long Frame Sync, Master Mode
Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)
PCM_BCLK
PCM_SYNC
PCM_OUT
5
PCM_IN
1
4
Bit 0
Bit 0
Bit 1
Bit 1
2
3
8
HIGH IMPEDANCE
6
7
Table 9: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Ref No.
1
2
3
4
5
6
7
8
Characteristics
PCM bit clock frequency
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
PCM_IN hold
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
Minimum
–
41
41
0
0
8
8
0
Typical
–
–
–
–
–
–
–
–
Maximum Unit
12
MHz
–
ns
–
ns
25
ns
25
ns
–
ns
–
ns
25
ns
Broadcom^®
October 15, 2014 • 4354-DS109-R
BROADCOM CONFIDENTIAL
Page 49