EP2S30F484C4N Datasheet, PDF (97/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
V_CCIO level independently. Each bank also has dedicated VREF pins to
support the voltage-referenced standards (such as SSTL-2). The PLL
banks utilize the adjacent VREF group when voltage-referenced
standards are implemented. For example, if an SSTL input is
implemented in PLL bank 10, the voltage level at VREFB7 is the reference
voltage level for the SSTL input.
I/O pins that reside in PLL banks 9 through 12 are powered by the
VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The EP2S60F484,
EP2S60F780, EP2S90H484, EP2S90F780, and EP2S130F780 devices do not
support PLLs 11 and 12. Therefore, any I/O pins that reside in bank 11 are
powered by the VCCIO3 pin, and any I/O pins that reside in bank 12 are
powered by the VCCIO8 pin.
Each I/O bank can support multiple standards with the same V_CCIO for
input and output pins. Each bank can support one V_REF voltage level. For
example, when V_CCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and
3.3-V PCI for inputs and outputs.
On-Chip Termination
Stratix II devices provide differential (for the LVDS or HyperTransport
technology I/O standard), series, and parallel on-chip termination to
reduce reflections and maintain signal integrity. On-chip termination
simplifies board design by minimizing the number of external
termination resistors required. Termination can be placed inside the
package, eliminating small stubs that can still lead to reflections.
Stratix II devices provide four types of termination:
■ Differential termination (R_D)
■ Series termination (R_S) without calibration
■ Series termination (R_S) with calibration
■ Parallel termination (R_T) with calibration
Altera Corporation
May 2007
2–89
Stratix II Device Handbook, Volume 1