EP2S30F484C4N Datasheet, PDF (155/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

DC & Switching Characteristics
Table 5–31. Series & Differential On-Chip Termination Specification for Left & Right I/O Banks
Symbol
Description
Conditions
25-Ω R_S
3.3/2.5
Internal series termination without V_{C CI O} = 3.3/2.5 V
calibration (25-Ω setting)
50-Ω R_S
Internal series termination without V_{C CI O} = 3.3/2.5/1.8 V
3.3/2.5/1.8 calibration (50-Ω setting)
50-Ω R_S 1.5 Internal series termination without V_{C CI O} = 1.5 V
calibration (50-Ω setting)
R_D
Internal differential termination for ^VC CI O ^{= 2.5 V}
LVDS or HyperTransport technology
(100-Ω setting)
Resistance Tolerance
Commercial Industrial
Max
Max
Unit
±30
±30
%
±30
±30
%
±36
±36
%
±20
±25
%
Pin Capacitance
Table 5–32 shows the Stratix II device family pin capacitance.
Table 5–32. Stratix II Device Capacitance Note (1)
Symbol
Parameter
Typical Unit
C_{I O T B}
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
5.0
pF
C_{I O L R}
Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including high-
6.1
pF
speed differential receiver and transmitter pins.
C_{C L K T B}
Input capacitance on top/bottom clock input pins: CLK[4..7] and
CLK[12..15].
6.0
pF
C_{C L K L R}
Input capacitance on left/right clock inputs: CLK0, CLK2, CLK8, CLK10.
6.1
pF
C_{C L K L R +}
Input capacitance on left/right clock inputs: CLK1, CLK3, CLK9, and
CLK11.
3.3
pF
C_{O U T F B}
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 9, 10, 11, and 12.
6.7
pF
Note to Table 5–32:
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5pF
Altera Corporation
April 2011
5–19
Stratix II Device Handbook, Volume 1