EP2S30F484C4N Datasheet, PDF (229/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

DC & Switching Characteristics
Table 5–93. Fast PLL Specifications
Name
Description
Min
Typ
f_{I N}
f_{I N P F D}
f_{I N D U T Y}
t_{I N J I T T E R}
f_{V C O}
f_{O U T}
f_{O U T _ I O}
f_{S C A N C L K}
t_{C O N F I G P L L}
Input clock frequency (for -3 and -4 speed
grade devices)
Input clock frequency (for -5 speed grade
devices)
Input frequency to the PFD
Input clock duty cycle
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤ 2 MHz
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 2 MHz
Upper VCO frequency range for –3 and –4
speed grades
Upper VCO frequency range for –5 speed
grades
Lower VCO frequency range for –3 and –4
speed grades
Lower VCO frequency range for –5 speed
grades
PLL output frequency to GCLK or RCLK
PLL output frequency to LVDS or DPA clock
PLL clock output frequency to regular I/O
pin
Scanclk frequency
Time required to reconfigure scan chains
for fast PLLs
16.08
16.08
16.08
40
300
300
150
150
4.6875
150
4.6875
0.5
1.0
75/f_{S C A N C L K}
f_{C L B W}
PLL closed-loop bandwidth
t_{L O C K}
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
t_{P L L _ P S E R R}
Accuracy of PLL phase shift
t_{A R E S E T}
Minimum pulse width on areset signal.
t_{A R E S E T _ R E C O N F I G} Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the
PLL after scandone goes high.
1.16
10
500
5.00
0.03
Max Unit
717 MHz
640 MHz
500 MHz
60
%
ns (p-p)
ns (p-p)
1,040 MHz
840 MHz
520 MHz
420 MHz
550
1,040
(1)
MHz
MHz
MHz
100 MHz
ns
28.00
1.00
MHz
ms
±15
ps
ns
ns
Note to Table 5–93:
(1) Limited by I/O f_{M A X} . See Table 5–77 on page 5–67 for the maximum.
Altera Corporation
April 2011
5–93
Stratix II Device Handbook, Volume 1