EP2S30F484C4N Datasheet, PDF (225/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

DC & Switching Characteristics
Table 5–90 shows the high-speed I/O timing specifications for -4 speed
grade Stratix II devices.
Table 5–90. High-Speed I/O Specifications for -4 Speed Grade Notes (1), (2)
Symbol
Conditions
-4 Speed Grade
Unit
Min Typ Max
f_{H SC L K} (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology) 16
f_{H S C L K} = f_{H S D R} / W
(3)
W = 1 (SERDES bypass, LVDS only)
16
520
MHz
500
MHz
W = 1 (SERDES used, LVDS only)
150
717
MHz
f_{H S D R} (data rate)
J = 4 to 10 (LVDS, HyperTransport technology) 150
J = 2 (LVDS, HyperTransport technology)
(4)
J = 1 (LVDS only)
(4)
f_{H S D R D PA} (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology) 150
TCCS
All differential standards
-
1,040
760
500
1,040
200
Mbps
Mbps
Mbps
Mbps
ps
SW
All differential standards
330
-
ps
Output jitter
190
ps
Output t_{R I S E}
Output t_{FA L L}
t_DUTY
DPA run length
All differential I/O standards
All differential I/O standards
160
ps
180
ps
45 50 55
%
6,400
UI
DPA jitter tolerance
Data channel peak-to-peak jitter
0.44
UI
DPA lock time
Standard
Training
Pattern
Transition
Density
Number of
repetitions
SPI-4
0000000000
10%
256
1111111111
Parallel Rapid I/O 00001111
25%
256
10010000
50%
256
Miscellaneous
10101010
100% 256
01010101
256
Notes to Table 5–90:
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
Altera Corporation
April 2011
5–89
Stratix II Device Handbook, Volume 1