EP2S30F484C4N Datasheet, PDF (78/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

I/O Structure
■ Output drive strength control
■ Tri-state buffers
■ Bus-hold circuitry
■ Programmable pull-up resistors
■ Programmable input and output delays
■ Open-drain outputs
■ DQ and DQS I/O pins
■ Double data rate (DDR) registers
The IOE in Stratix II devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 2–46 shows the Stratix II IOE structure. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
2–70
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007