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EP2S30F484C4N Datasheet, PDF (71/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet | |||
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Stratix II Architecture
Figure 2â43 shows the global and regional clocking from enhanced PLL
outputs and top and bottom CLK pins. The connections to the global and
regional clocks from the top clock pins and enhanced PLL outputs is
shown in Table 2â11. The connections to the clocks from the bottom clock
pins is shown in Table 2â12.
Altera Corporation
May 2007
2â63
Stratix II Device Handbook, Volume 1
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