EP2S30F484C4N Datasheet, PDF (227/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

DC & Switching Characteristics
PLL Timing
Specifications
Tables 5–92 and 5–93 describe the Stratix II PLL specifications when
operating in both the commercial junction temperature range (0 to 85 °C)
and the industrial junction temperature range (–40 to 100 °C).
Table 5–92. Enhanced PLL Specifications (Part 1 of 2)
Name
f_{I N}
f_{I N P F D}
f_{I N D U T Y}
f_{E I N D U T Y}
t_{I N J I T T E R}
t_{O U T J I T T E R}
t_{F C O M P}
f_{O U T}
t_{O U T D U T Y}
f_{S C A N C L K}
t_{C O N F I G P L L}
f_{O U T _ E X T}
Description
Min
Typ
Max
Unit
Input clock frequency 2
500
MHz
Input frequency to the 2
PFD
Input clock duty cycle 40
420
MHz
60
%
External feedback
40
input clock duty cycle
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth ≤
0.85 MHz
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth >
0.85 MHz
Dedicated clock
output period jitter
External feedback
compensation time
Output frequency for 1.5
internal global or
(2)
regional clock
Duty cycle for external 45
clock output (when set
to 50%).
Scanclk frequency
60
%
0.5
ns (p-p)
1.0
ns (p-p)
250 ps for ≥ 100 MHz outclk ps or mUI
25 mUI for < 100 MHz outclk (p-p)
10
ns
550.0
MHz
50
55
%
100
MHz
Time required to
reconfigure scan
chains for enhanced
PLLs
PLL external clock
output frequency
174/f_{S C A N C L K}
1.5
(2)
550.0 (1)
ns
MHz
Altera Corporation
April 2011
5–91
Stratix II Device Handbook, Volume 1