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EP2S30F484C4N Datasheet, PDF (63/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet | |||
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Stratix II Architecture
Figure 2â38. Regional Clock Control Blocks
PLL Counter
Outputs (3)
CLKp CLKn
Pin Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2â38:
(1) These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
(2) Only the CLKn pins on the top and bottom of the device feed to regional clock select
blocks.The clock outputs from corner PLLs cannot be dynamically selected
through the global clock control block.
(3) The clock outputs from corner PLLs cannot be dynamically selected through the
global clock control block.
Altera Corporation
May 2007
2â55
Stratix II Device Handbook, Volume 1
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