EP2S30F484C4N Datasheet, PDF (45/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
Figure 2–25. M-RAM Block LAB Row Interface Note (1)
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
L0
L1
L2 _{Port A}
L3
L4
L5
M-RAM Block
R0
R1
Port B ^R2
R3
R4
R5
LAB Interface
Blocks
LABs in Row
M-RAM Boundary
Note to Figure 2–25:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
LABs in Row
M-RAM Boundary
Altera Corporation
May 2007
2–37
Stratix II Device Handbook, Volume 1