EP2S30F484C4N Datasheet, PDF (217/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II
non-DDIO row output clock on a –3 device ranges from 47.5% to 52.5%.
Table 5–81. Maximum DCD for Non-DDIO Output on Column I/O
Pins Note (1)
Column I/O Output
Maximum DCD for Non-DDIO Output
Standard I/O
Standard
-3 Devices
Unit
-4 & -5 Devices
3.3-V LVTTL
190
220
ps
3.3-V LVCMOS
140
175
ps
2.5 V
125
155
ps
1.8 V
80
110
ps
1.5-V LVCMOS
185
215
ps
SSTL-2 Class I
105
135
ps
SSTL-2 Class II
100
130
ps
SSTL-18 Class I
90
115
ps
SSTL-18 Class II
70
100
ps
1.8-V HSTL
80
Class I
110
ps
1.8-V HSTL
80
Class II
110
ps
1.5-V HSTL
85
Class I
115
ps
1.5-V HSTL
50
Class II
80
ps
1.2-V HSTL (2)
170
-
ps
LVPECL
55
80
ps
Notes to Table 5–81:
(1) The DCD specification is based on a no logic array noise condition.
(2) 1.2-V HSTL is only supported in -3 devices.
Altera Corporation
April 2011
5–81
Stratix II Device Handbook, Volume 1