EP2S30F484C4N Datasheet, PDF (21/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
datae1 and dataf1 are utilized, the output drives to register1
and/or bypasses register1 and drives to the interconnect using the
bottom set of output drivers. The Quartus II Compiler automatically
selects the inputs to the LUT. Asynchronous load data for the register
comes from the datae or dataf input of the ALM. ALMs in normal
mode support register packing.
Figure 2–9. 6-Input Function in Normal Mode Notes (1), (2)
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
datae1
dataf1
(2)
These inputs are available for register packing.
DQ
reg0
DQ
reg1
To general or
local routing
To general or
local routing
To general or
local routing
Notes to Figure 2–9:
(1) If datae1 and dataf1 are used as inputs to the six-input function, then datae0
and dataf0 are available for register packing.
(2) The dataf1 input is available for register packing only if the six-input function is
un-registered.
Extended LUT Mode
The extended LUT mode is used to implement a specific set of
seven-input functions. The set must be a 2-to-1 multiplexer fed by two
arbitrary five-input functions sharing four inputs. Figure 2–10 shows the
template of supported seven-input functions utilizing extended LUT
mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in Figure 2–10 occur naturally
in designs. These functions often appear in designs as “if-else” statements
in Verilog HDL or VHDL code.
Altera Corporation
May 2007
2–13
Stratix II Device Handbook, Volume 1