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| EP2S30F484C4N Datasheet, PDF (145/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet | |||
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DC & Switching Characteristics
Table 5â12. LVPECL Specifications
Symbol
VCCIO (1)
VID
VICM
VOD
VOCM
RL
Parameter
Conditions
I/O supply voltage
Input differential voltage
swing (single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode
voltage
Receiver differential input
resistor
RL = 100 Ω
RL = 100 Ω
Minimum
3.135
300
1.0
525
1,650
90
Typical
3.300
600
100
Maximum Unit
3.465
V
1,000 mV
2.5
V
970
mV
2,250 mV
110
Ω
Note to Table 5â12:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.
Table 5â13. HyperTransport Technology Specifications
Symbol
Parameter
Conditions
VCCIO
VID
VICM
VOD
Î VOD
VOCM
Î VOCM
RL
I/O supply voltage for left and
right I/O banks (1, 2, 5, and 6)
Input differential voltage swing RL = 100 Ω
(single-ended)
Input common mode voltage RL = 100 Ω
Output differential voltage
(single-ended)
RL = 100 Ω
Change in VOD between high RL = 100 Ω
and low
Output common mode voltage RL = 100 Ω
Change in VOCM between high RL = 100 Ω
and low
Receiver differential input
resistor
Minimum
2.375
300
385
400
440
90
Typical
2.500
600
600
600
600
100
Maximum Unit
2.625
V
900
mV
845
mV
820
mV
75
mV
780
mV
50
mV
110
Ω
Table 5â14. 3.3-V PCI Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO
VIH
Output supply voltage
High-level input voltage
Conditions
Minimum
3.0
0.5 Ã VCCIO
Typical
3.3
Maximum Unit
3.6
V
VCCIO + 0.5 V
Altera Corporation
April 2011
5â9
Stratix II Device Handbook, Volume 1
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