EP2S30F484C4N Datasheet, PDF (27/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
Figure 2–14. Example of a 3-bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0'
3-Bit Add Example
1st stage add is
implemented in LUTs.
2nd stage add is
implemented in adders.
X2 X1 X0
Y2 Y1 Y0
+ Z2 Z1 Z0
S2 S1 S0
+ C2 C1 C0
R3 R2 R1 R0
ALM Implementation
ALM 1
3-Input S0
LUT
X0
Y0
3-Input _C0
Z0
LUT
carry_in = '0'
R0
Binary Add
Decimal
X1
Equivalents
Y1
Z1
3-Input S1
LUT
110
6
R1
101
5
+0 1 0
+2
3-Input C1
LUT
001
1
+1 1 0
1101
+ 2x6
13
ALM 2
3-Input S2
LUT
R2
X2
3-Input C2
Y2
Z2
LUT
3-Input '0'
LUT
R3
3-Input
LUT
Altera Corporation
May 2007
Shared Arithmetic Chain
In addition to the dedicated carry chain routing, the shared arithmetic
chain available in shared arithmetic mode allows the ALM to implement
a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or fifth ALM in
an LAB. The Quartus II Compiler creates shared arithmetic chains longer
than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking
LABs together automatically. For enhanced fitting, a long shared
2–19
Stratix II Device Handbook, Volume 1