EP2S30F484C4N Datasheet, PDF (116/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Stratix II JTAG Instructions
JTAG Instruction
SAMPLE/PRELOAD
EXTEST(1)
BYPASS
USERCODE
IDCODE
HIGHZ (1)
CLAMP (1)
ICR instructions
PULSE_NCONFIG
CONFIG_IO (2)
SignalTap II
instructions
Instruction Code
Description
00 0000 0101
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
00 0000 1111
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
11 1111 1111
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
00 0000 0111
Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
00 0000 0110 Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
00 0000 1011
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
00 0000 1010
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring a Stratix II device via the JTAG port with a
USB Blaster, MasterBlaster™, ByteBlasterMV™, or ByteBlaster II
download cable, or when using a .jam or .jbc via an embedded
processor or JRunner.
00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration
even though the physical pin is unaffected.
00 0000 1101
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during configuration.
Once issued, the CONFIG_IO instruction holds nSTATUS low to
reset the configuration device. nSTATUS is held low until the IOE
configuration register is loaded and the TAP controller state
machine transitions to the UPDATE_DR state.
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
Notes to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information on using the CONFIG_IO instruction, see the MorphIO: An I/O Reconfiguration Solution for
Altera Devices White Paper.
3–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007