EP2S30F484C4N Datasheet, PDF (54/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Digital Signal Processing Block
Figure 2–30. DSP Block Interface to Interconnect
C4 Interconnect
Direct Link Interconnect
from Adjacent LAB
R4 Interconnect
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
LAB
36
18
36
DSP Block
Row Structure
LAB
16
16
12
Control
36
A[17..0]
OA[17..0]
36
B[17..0]
OB[17..0]
Row Interface
Block
DSP Block to
LAB Row Interface
Block Interconnect Region
36 Inputs per Row
36 Outputs per Row
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed/unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface.
2–46
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007