EP2S30F484C4N Datasheet, PDF (92/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

I/O Structure
Table 2–15 shows the possible settings for the I/O standards with drive
strength control.
Table 2–15. Programmable Drive Strength Note (1)
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
I_OH / I_OL Current Strength
Setting (mA) for Column
I/O Pins
24, 20, 16, 12, 8, 4
24, 20, 16, 12, 8, 4
16, 12, 8, 4
12, 10, 8, 6, 4, 2
8, 6, 4, 2
12, 8
24, 20, 16
12, 10, 8, 6, 4
20, 18, 16, 8
12, 10, 8, 6, 4
20, 18, 16
12, 10, 8, 6, 4
20, 18, 16
I_OH / I_OL Current Strength
Setting (mA) for Row I/O
Pins
12, 8, 4
8, 4
12, 8, 4
8, 6, 4, 2
4, 2
12, 8
16
10, 8, 6, 4
-
12, 10, 8, 6, 4
-
8, 6, 4
-
Note to Table 2–15:
(1) The Quartus II software default current setting is the maximum setting for each
I/O standard.
Open-Drain Output
Stratix II devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Bus Hold
Each Stratix II device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can weakly hold the signal on an I/O pin at its
last-driven state. Since the bus-hold feature holds the last-driven state of
the pin until the next input signal is present, you do not need an external
pull-up or pull-down resistor to hold a signal level when the bus is
tri-stated.
2–84
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007