EP2S30F484C4N Datasheet, PDF (58/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

PLLs & Clock Networks
Figure 2–32. Regional Clocks
RCLK[31..28] RCLK[27..24]
CLK[15..12]
RCLK[3..0]
CLK[3..0]
RCLK[7..4]
RCLK[23..20]
CLK[11..8]
RCLK[19..16]
CLK[7..4]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
PLLs or Core Logic within that Quadrant
RCLK[11..8] RCLK[15..12]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure 2–33. Corner PLLs cannot drive dual-regional clocks.
2–50
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007