EP2S30F484C4N Datasheet, PDF (222/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Duty Cycle Distortion
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 2 of 2) Note (1)
Row DDIO Output I/O
Standard
LVDS/ HyperTransport
technology
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Unit
-3 Device
-4 & -5 Device
180
180
ps
Note to Table 5–86:
(1) The DCD specification is based on a no logic array noise condition.
Table 5–87. Maximum DCD for DDIO Output on Column I/O with PLL in the
Clock Path Note (1)
Maximum DCD (PLL Output Clock Feeding
Column DDIO Output I/O
Standard
DDIO Clock Port)
Unit
-3 Device
-4 & -5 Device
3.3-V LVTTL
145
160
ps
3.3-V LVCMOS
100
110
ps
2.5V
85
95
ps
1.8V
85
100
ps
1.5-V LVCMOS
140
155
ps
SSTL-2 Class I
65
75
ps
SSTL-2 Class II
60
70
ps
SSTL-18 Class I
50
65
ps
SSTL-18 Class II
70
80
ps
1.8-V HSTL Class I
60
70
ps
1.8-V HSTL Class II
60
70
ps
1.5-V HSTL Class I
55
70
ps
1.5-V HSTL Class II
85
100
ps
1.2-V HSTL
155
-
ps
LVPECL
180
180
ps
Notes to Table 5–87:
(1) The DCD specification is based on a no logic array noise condition.
(2) 1.2-V HSTL is only supported in -3 devices.
5–86
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011