EP2S30F484C4N Datasheet, PDF (194/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 2 of 8)
I/O Standard
Drive
Strength
Parameter
LVCMOS
2.5 V
4 mA
t_{O P}
t_{D I P}
8 mA
t_{O P}
t_{D I P}
12 mA t_{O P}
t_{D I P}
16 mA t_{O P}
t_{D I P}
20 mA t_{O P}
t_{D I P}
24 mA t_{O P}
(1)
t_{D I P}
4 mA
t_{O P}
t_{D I P}
8 mA
t_{O P}
t_{D I P}
12 mA t_{O P}
t_{D I P}
16 mA t_{O P}
(1)
t_{D I P}
Minimum Timing
Industrial Commercial
-3
Speed
Grade
(3)
-3
Speed
Grade
(4)
-4
Speed
Grade
-5
Speed
Grade
Unit
1041
1091
2036 2136 2340 2448 ps
1061
1113
2102 2206 2416 2538 ps
952
999
1786 1874 2053 2153 ps
972
1021
1852 1944 2129 2243 ps
926
971
1720 1805 1977 2075 ps
946
993
1786 1875 2053 2165 ps
933
978
1693 1776 1946 2043 ps
953
1000
1759 1846 2022 2133 ps
921
965
1677 1759 1927 2025 ps
941
987
1743 1829 2003 2115 ps
909
954
1659 1741 1906 2003 ps
929
976
1725 1811 1982 2093 ps
1004
1053
2063 2165 2371 2480 ps
1024
1075
2129 2235 2447 2570 ps
955
1001
1841 1932 2116 2218 ps
975
1023
1907 2002 2192 2308 ps
934
980
1742 1828 2002 2101 ps
954
1002
1808 1898 2078 2191 ps
918
962
1679 1762 1929 2027 ps
938
984
1745 1832 2005 2117 ps
5–58
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011