EP2S30F484C4N Datasheet, PDF (95/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
Table 2–16. Stratix II Supported I/O Standards (Part 2 of 2)
I/O Standard
SSTL-2 Class I and II
Input Reference Output Supply Board Termination
Type
Voltage (V_REF) (V) Voltage (V_CCIO) (V) Voltage (V_TT) (V)
Voltage-referenced
1.25
2.5
1.25
Notes to Table 2–16:
(1) This I/O standard is only available on input and output column clock pins.
(2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock
pins in I/O banks 9,10, 11, and 12.
(3) V_CCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 9, 10, 11, and 12).
The clock input pins supporting LVDS on banks 3, 4, 7, and 8 use V_CCINT for LVDS input operations and have no
dependency on the V_CCIO level of the bank.
(4) 1.2-V HSTL is only supported in I/O banks 4,7, and 8.
f
For more information on I/O standards supported by Stratix II I/O
banks, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
Stratix II devices contain eight I/O banks and four enhanced PLL external
clock output banks, as shown in Figure 2–57. The four I/O banks on the
right and left of the device contain circuitry to support high-speed
differential I/O for LVDS and HyperTransport inputs and outputs. These
banks support all Stratix II I/O standards except PCI or PCI-X I/O pins,
and SSTL-18 Class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL
external clock output banks allow clock output capabilities such as
differential support for SSTL and HSTL.
Altera Corporation
May 2007
2–87
Stratix II Device Handbook, Volume 1