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EP2S30F484C4N Datasheet, PDF (110/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet | |||
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High-Speed Differential I/O with DPA Support
For high-speed source synchronous interfaces such as POS-PHY 4,
Parallel RapidIO, and HyperTransport, the source synchronous clock rate
is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols since the source synchronous clock does not
provide a byte or word boundary since the clock is one half the data rate,
not one eighth. The Stratix II deviceâs high-speed differential I/O
circuitry provides dedicated data realignment circuitry for user-
controlled byte boundary shifting. This simplifies designs while saving
ALM resources. You can use an ALM-based state machine to signal the
shift of receiver byte boundaries until a specified pattern is detected to
indicate byte alignment.
Fast PLL & Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left and right side of the device has one receiver channel and
one transmitter channel per LAB row. Figure 2â60 shows the fast PLL and
channel layout in the EP2S15 and EP2S30 devices. Figure 2â61 shows the
fast PLL and channel layout in the EP2S60 to EP2S180 devices.
Figure 2â60. Fast PLL & Channel Layout in the EP2S15 & EP2S30 Devices Note (1)
4
LVDS
Clock
4
2
Fast
PLL 1
DPA
Clock
Quadrant
Quadrant
DPA
Clock
4
LVDS
Clock
4
2
Fast
PLL 4
Fast
PLL 2
2
LVDS
4
Clock
DPA
Clock
Quadrant
Quadrant
Note to Figure 2â60:
(1) See Table 2â21 for the number of channels each device supports.
DPA
Clock
Fast
PLL 3
2
LVDS
Clock
4
2â102
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
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