EP2S30F484C4N Datasheet, PDF (12/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Logic Array Blocks
Figure 2–2. Stratix II LAB Structure
Row Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
ALMs
Direct link
interconnect from
adjacent block
Local Interconnect LAB
Direct link
interconnect to
adjacent block
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven
by column and row interconnects and ALM outputs in the same LAB.
Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM
blocks, or DSP blocks from the left and right can also drive an LAB's local
interconnect through the direct link connection. The direct link
connection feature minimizes the use of row and column interconnects,
providing higher performance and flexibility. Each ALM can drive
24 ALMs through fast local and direct link interconnects. Figure 2–3
shows the direct link connection.
2–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007