AK8140A Datasheet, PDF (9/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
over VDD1-4: 3.0 to 3.6V, VDDO1-2:1.7 to 3.6V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
CLK4 LVDS Output Parameter
Output Frequency
fout
Output Differential Voltage⁽¹⁾⁽²⁾
Vod
Offset Voltage⁽¹⁾⁽²⁾
Output Clock Rise Time ⁽¹⁾⁽²⁾
Output Clock Fall Time⁽¹⁾⁽²⁾
Vos
T_rise
T_fall
VDDO2=:2.3 to 3.6V,
CLK4MOD=”1”
VDDO2=:1.7 to 1.9V,
CLK4MOD=”0”
0.2*VDDO2 → 0.8*VDDO2
0.2*VDDO2 → 0.8*VDDO2
When ODIV4 divides the
PLL1/2 clock
Output Clock Duty Cycle⁽¹⁾⁽²⁾
When ODIV4 divides the
Input Bypass clock by even
dividing value
When ODIV4 divides the
Input Bypass clock by odd
dividing value
(1) Design Value
(2) LVDS clock measured at the circuit shown in Figure.4
MIN
250
1.125
0.685
45
45
20
TYP
350
1.240
0.800
0.2
0.2
50
50
MAX
230
450
1.375
0.935
55
55
80
Unit
MHz
mVpp
V
ns
ns
%
%
%
CLK4p
OUTP
Z₀=100 Differential 100
CLK4n
OUTN
AK8140A
Figure.4 CLK4 LVDS Clock measurement circuit
draft-E-06
-9-
Sep -12