AK8140A Datasheet, PDF (33/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

●Address：2１h PLL１ Input Clock Selection/ fVCO1 range
Address
D7
Data
D6
D5
D4
D3
D2
21h
INPUT
VCO1
VCO1
VCO1
VCO1
－
_CK1
_RANG0[1] _RANG0[0] _RANG1[1] _RANG1[0]
INPUT_CK1 ： PLL1Input Clock Selection (MUX5)
INPUT_CK1
0
1
PLL1Input Clock
Input Clock
（Crystal Oscillation
or
External clock input）
fvco2
PLL2 output clock
AK8140A
D1
D0
－
－
VCO1_RANGEn[1:0] ： fVCO1 range selection n=0/1
“VCO1_RANGEn[1:0]” selects the fVCO1 frequency range. fVCO1 frequency can be set
according to Frequency Setting Procedure on page 10.
VCO1_RANGEn[1:0]
00
01
10
11
fVCO1 range
fVCO1 < 300MHz
300MHz <= fvco1 <
370MHz
370MHz <= fvco1
370MHz <= fvco1
●Address：22h/28h、23h/29h、24h/2Ah NDIV1 fractional part setting
Address
D7
D6
D5
Data
D4
D3
D2
22h
27h
23h
28h
FRACn[15] FRACn[14] FRACn[13] FRACn[12] FRACn[11] FRACn[10]
24h
29h
FRACn[7] FRACn[6] FRACn[5] FRACn[4] FRACn[3] FRACn[2]
FRACn[17:0] settings are updated after writing register 24h/20h.
Setting procedure should be (1)22h/27h ,( 2)23h/28h, and then (3)24h/29h
D1
FRACn[17]
FRACn[9]
FRACn[1]
D0
FRACn[16]
FRACn[8]
FRACn[0]
FRACn [17:0] ： NDIV1 fractional part setting n=0/1
NDIV1 fractional part can be set according to Frequency Setting Procedure on page 10.
Fractional part of N is expressed by A/218. Here, the numerator A is defined by FRAC bits. FRAC
is treated as 2’s Complement which is able to set from -217 up to +217. Consequently, it is
possible to set from -0.5 to +0.5 for fractional part of N.
draft-E-06
- 33 -
Sep -12