AK8140A Datasheet, PDF (38/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
PLL2 Configuration Register
PLL2 Block Diagram is as the following Figure.
Please set PLL2 parameter according to. Frequency Setting Procedure on page 10.
PLL2 has two Frequency mode predefined as PLL2_0 or PLL2_1 and selected by S0/S1/S2 pin or
S[2:0] bits (Address:00h). see on page 10more information about Frequency selection.
fin2
MDIV2 Setting
(31h/35h)
NDIV2 Setting
(32h-34h/36h-38h)
fVCO2 range
(31h/35h)
Figure PLL2 Block Diagram
●Address：30h PLL2 Output Frequency selection
Data
Address
D7
D6
D5
D4
D3
30h _{FS2_0 FS2_1 FS2_2 FS2_3 FS2_4}
FS2_x (x=0～7)： PLL１Output Frequency selection
D2
FS2_5
D1
FS2_6
D0
FS2_7
The output frequency of PLL2 is chosen from two setups，PLL2_0 or PLL2_1.
FS2_x
0
1
PLL2 Frequency
PLL2_0
Predefined by address:31h～34h
PLL2_1
Predefined by address:35h～38h
Sep -12
- 38 -
draft-E-06