AK8140A Datasheet, PDF (21/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

07h
CLK2_4
ï¼»1]
CLK2_4
ï¼»0]
CLK2_
5ï¼»1]
CLK2_5
ï¼»0]
CLK2_6
ï¼»1]
CLK2_6
ï¼»0]
CLK2_
7ï¼»1]
AK8140A
CLK2_7
ï¼»0]
0
0
0
0
0
0
0
0
08h
09h
CLK3_0
ï¼»1]
CLK3_0
ï¼»0]
CLK3_1
ï¼»1]
CLK3_1
ï¼»0]
CLK3_2
ï¼»1]
CLK3_2
ï¼»0]
CLK3_3
ï¼»1]
CLK3_3
ï¼»0]
0
CLK3_4
ï¼»1]
0
CLK3_4
ï¼»0]
0
CLK3_5
ï¼»1]
0
CLK3_5
ï¼»0]
0
CLK3_6
ï¼»1]
0
CLK3_6
ï¼»0]
0
CLK3_7
ï¼»1]
0
CLK3_7
ï¼»0]
CLK3
Output State
Setting
0
0
0
0
0
0
0
0
0Ah
0Bh
CLK4_0
ï¼»1]
CLK4_0
ï¼»0]
CLK4_1
ï¼»1]
CLK4_1
ï¼»0]
CLK4_2
ï¼»1]
CLK4_2
ï¼»0]
CLK4_3
ï¼»1]
CLK4_3
ï¼»0]
0
0
0
CLK4_4
ï¼»1]
CLK4_4
ï¼»0]
CLK4_5
ï¼»1]
0
CLK4_
5ï¼»0]
0
CLK4_6
ï¼»1]
0
CLK4_6
ï¼»0]
0
CLK4_7
ï¼»1]
0
CLK4_7
ï¼»0]
CLK4
Output State
Setting
0
0
0
0
0
0
0
0
0Ch
MUX1
[1]
0
MUX1
[0]
0
MUX2
[1]
0
MUX2
[0]
0
MUX3
[1]
0
MUX3
[0]
0
MUX4
[1]
0
MUX4
0]
0
MUX1～4
Selection
0Dh
Reserved Reserved Reserved Reserved
CLK1
MOD
DIV2_
BYPASS1
ODIV_1
[9]
ODIV_1
[8]
Output Buffer1
Drivability
－
－
－
－
0
0
0
0
ODIV1 Setting
draft-E-06
- 21 -
Sep -12