AK8140A Datasheet, PDF (24/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
OSC_DIS ： Crystal Oscillator Circuit Enable/Disable Setting（MUX0）
Set the register followed by ICLK source, as explained in the following table.
OSC_DIS
0
1
Crystal Oscillator Circuit State
Enable（ICLK=Crystal）
Disable（ICLK=Ext-in）
R/W ： User arbitrarily programmable bits（D3～D0）
User can freely program these bits if necessary.
●Address：03h
Address
D7
03h _Reserved
D6
Reserved
Data
D5
D4
D3
D2
D1
D0
PWDN SLV_ADD1 Reserved CLK4_CMOS SPICON EEWRITE
PWDN ： Device Power Down control
.
When set PWDN bit to ’1’, only PLL1/2, ODIVn, is powered down. Register settings are
unchanged.
CLKn output state is followed by CLKn output state selection(Address:04h-0Bh) when the
device is powered down by this bit. *1
PWDN
Device Setting
0
Device Active
1
Device Powered down*1
*1 It becomes CLKn=L, when CLKn output state is set to ‘01’ as “CLK
enabled”.
SLV_ADD1 ： Slave Address Bits A1 Selection
SLV_ADD1 sets the A1 of the Slave Receiver Address.
*The default setting SLV_ADD1= ‘0’ appears after power is supplied or after power-down/up
sequence until it is reprogrammed to a different setting.
* See page 25 for more information about Slave Address setting.
SLV_ADD1
Device Setting
0
A1 of Slave Address ：0
1
A1 of Slave Address ：1 *1
* 1 Default state is A1=’0’
Sep -12
- 24 -
draft-E-06