AK8140A Datasheet, PDF (28/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
ODIVn Dividing Value Setting （ODIV_n/DIV2_BYPASSn）
The Dividing value of ODIVn is decided by “Frequency setting procedure” on page 10.
(1)The case ODIVn divides the clock signal of Input Bypass. (MUXn = ‘01’)
Set ODIVn dividing value according to explanation below, when ODIVn divides a clock signal
of Input Bypass.
ODIVn configuration is as the following Figure.
ODIVn
-2Divider
ODIV_n
CLKn
*ODIVn is calculated number by “Frequency setting procedure” on page 10.
・When set ODIVn dividing Value = 2 or odd number：
→Bypass ODIVn_2 Divider ,ODIV_n is the same number as ODIVn
Example1：ODIVn=3
Bypass ODIVn_2 Divider (DIV2_BYPASSn = ‘1’)
ODIV_n = ODIVn=3
・When set ODIVn dividing Value even number beyond 4
→Using ODIVn_2 Divider, ODIV_n = ODIVn/2
DIV2_Bypassn _{ODIV_n}
Exam_(B0p_Dyplhea_-1_1s：_3sOhO)DDIVIVnn=_120_{(0DDihv-i1d3ehr)(DIV2_BYPASSn = ‘0’)}
ODIV_n = ODIVn/2 =5
（2）The case ODIVn divides clock signal of PLL1 or PLL2 (MUXn =’10’ or ‘11’)
Set ODIVn dividing value according to explanation below, when ODIVn divides clock signal
of PLL1 or PLL2
・When ODIVn divides fvco1 （MUXn=’10’）：
→ODIVn = ODIVn (calculated value )/2
・When ODIVn divides fvco2 （MUXn=’10’）：
→ODIVn = ODIVn (calculated value )
Sep -12
- 28 -
draft-E-06