AK8140A Datasheet, PDF (8/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
over VDD1-4: 3.0 to 3.6V, VDDO1-2:1.7 to 3.6V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP MAX Unit
LVCMOS output parameter
Output Frequency
fout
Pin:CLK1-4
160
MHz
Pin: CLK1-4
High Level Output Voltage
VOH
IOH=-4mA
0.8*VDDO1, 2
V
Low level Output Voltage
Output Clock Rise Time ^(1)(2)(3)(4)
Output Clock Fall Time ^(1)(2)(3)(4)
VOL
T_rise
T_fall
Pin: CLK1-4
IOL=+4mA
Pin:CLK1-3
with Load cplclk=10pF(upper),
25pF(lower)
0.2*VDDO1, 2 → 0.8*VDDO1, 2
Pin:CLK4, VDDO2=3.3V
with Load Cplclk=10pF
0.2*VDDO2 → 0.8*VDDO2
Pin:CLK1-3
with Load Cplclk=10pF(upper),
25pF(lower)
0.2*VDDO1, 2 → 0.8*VDDO1, 2
Pin:CLK4, VDDO2=3.3V
with Load Cplclk=10pF
0.2*VDDO2 → 0.8*VDDO2
0.2*VDDO1, 2 V
0.7
1.2
Ns
0.3
0.7
1.2
Ns
0.3
Pin:CLK1, 2, 3, 4
When ODIVn divides the PLL1/2
45
50
55
clock.
Output Clock Duty Cycle ⁽¹⁾⁽²⁾
Pin:CLK1, 2, 3, 4
When ODIVn divides the Input
Bypass clock by even dividing
45
50
55
%
value.
Pin:CLK1, 2, 3, 4
When ODIVn divides the Input
Bypass clock by odd dividing
20
80
value.
(1) Design Value
(2) With the load describes on page5.
(3) When VDDO1/2=1.8V :CLKnMOD(n=1-3)=‘0’，when VDDO1/2=3.3V, CLKnMOD(n=1-3) =‘1’.
(4) When VDDO1/2=3.3V :CLK4MOD=‘1’.
Sep -12
draft-E-06
-8-