AK8140A Datasheet, PDF (32/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
PLL1 Configuration Register
PLL1 Block Diagram is as the following Figure.
Please set PLL１ parameter according to .
PLL1 has two Frequency mode predefined as PLL1_0 or PLL1_1 and selected by S0/S1/S2 pin
or S[2:0] bits (Address:00h). Refer to Programmable Control pin setting on page 14 for more
information about Frequency selection.
PLL1
Input CLK
(21h)
MDIV1 Setting NDIV1 Setting
(26h/28h)
(22h-25h, 27h-2Ah)
Figure PLL1 Block Diagram
fVCO1 range
(21h)
●Address：20h PLL１Output Frequency selection
Data
Address
D7
D6
D5
D4
D3
20h
FS1_0
FS1_1
FS1_2
FS1_3
FS1_4
FS1_x（x=0～7） ： PLL１Output Frequency selection
D2
FS1_5
D1
FS1_6
The output frequency of PLL is chosen from two setups ，PLL1_0 and PLL1_1.
FS1_x
0
1
PLL1 Frequency
PLL1_0
Predefined by address:21h, 22h～26h
PLL1_1
Predefined by address:21h, 27h～2Bh
D0
FS1_7
Sep -12
- 32 -
draft-E-06