AK8140A Datasheet, PDF (31/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

■PLL1 Configuration Register
AK8140A
Address
Data
Remarks
D7
D6
D5
D4
D3
D2
D1
D0
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
FS1_0
0
INPUT
_CK1
0
FS1_1
FS1_2
FS1_3
FS1_4
0
VCO1_
RANG0[1]
0
VCO1_
RANG0[0]
0
VCO1_
RANG1[1]
0
VCO1_
RANG1[0]
0
0
0
0
FS1_5
0
Reserved
－
FS1_6
0
Reserved
－
FS1_7
0
Reserved
－
PLL1 Frequency
Selection
PLL1 Input Clock
Selection
fVCO1 Range
Reserved Reserved Reserved Reserved Reserved Reserved
FRAC0
[17]
FRAC0
[16]
－
－
－
－
－
－
0
0
FRAC0
[15]
0
FRAC0
[14]
0
FRAC0
[13]
0
FRAC0
[12]
0
FRAC0
[11]
0
FRAC0
[10]
0
FRAC0
[9]
0
FRAC0
[8]
0
PLL1_0
NDIV1 Fractional
Part Setting
FRAC0
[7]
FRAC0
[6]
FRAC0
[5]
FRAC0
[4]
FRAC0
[3]
FRAC0
[2]
FRAC0
[1]
FRAC0
[0]
0
0
0
0
0
0
0
0
Reserved
－
MDIVC0
[3]
INT0[6]
0
MDIVC0
[2]
0
0
INT0[5]
0
MDIVC0
[1]
0
INT0[4]
0
MDIVC0
[0]
0
INT0[3]
0
MDIVP0
[3]
0
INT0[2]
0
MDIVP0
[2]
0
INT0[1]
0
MDIVP0
[1]
0
INT0[0]
0
MDIVP0
[0]
0
PLL1_0
NDIV1 Integral Part
Setting
PLL1_0
MDIV1 Setting
Reserved Reserved Reserved Reserved Reserved Reserved
－
－
－
－
－
－
FRAC1
[17]
0
FRAC1
[16]
0
FRAC1
[15]
0
FRAC1
[14]
0
FRAC1
[13]
0
FRAC1
[12]
0
FRAC1
[11]
0
FRAC1
[10]
0
FRAC1
[9]
0
FRAC1
[8]
0
PLL1_1
NDIV1 Fractional
Part Setting
FRAC1
[7]
FRAC1
[6]
FRAC1
[5]
FRAC1
[4]
FRAC1
[3]
FRAC1
[2]
FRAC1
[1]
FRAC1
[0]
0
0
0
0
0
0
0
0
Reserved
－
MDIVC1
[3]
INT1[6]
0
MDIVC1
[2]
0
0
INT1[5]
0
MDIVC1
[1]
0
INT1[4]
0
MDIVC1
[0]
0
INT1[3]
INT1[2]
0
MDIVP1
[3]
0
MDIVP1
[2]
0
0
INT1[1]
0
MDIVP1
[1]
0
INT1[0]
0
MDIVP1
[0]
0
PLL1_1
NDIV1 Integral Part
Setting
PLL1_1
MDIV1 Setting
draft-E-06
- 31 -
Sep -12