AK8140A Datasheet, PDF (20/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
■Generic Configuration Register
Generic Configuration Register(Address：00h～12h)
Data
Addres
Remarks
s
D7
D6
D5
D4
D3
D2
D1
D0
Reserved Reserved Reserved Reserved Reserved
S[2]
S[1]
S[0]
Device Control
00h
Setting for
－
－
－
－
－
0
0
0
SDA/SCL mode
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
01h
-
0
0
0
0
0
0
0
0
02h
03h
RID[1]
RID[0]
OSC_DIS Reserved
R/W
R/W
R/W
R/W
0
0
0
Reserved Reserved
PWDN
0
SLV_
ADD1
－
－
Reserved
CLK4_
CMOS
－
SPICON
－
Device overall
SPICON_S ^Setting
ET
0
0
0
0
0
0
0
0
04h
05h
06h
CLK1_0
[1]
CLK1_0
[0]
CLK1_1
ï¼»1]
CLK1_1
ï¼»0]
CLK1_2
ï¼»1]
CLK1_2
ï¼»0]
CLK1_3
ï¼»1]
CLK1_
ï¼»0]
0
CLK1_4
ï¼»1]
0
CLK1_4
ï¼»0]
0
CLK1_5
ï¼»1]
0
CLK1_5
ï¼»0]
0
CLK1_6
ï¼»1]
0
CLK1_6
ï¼»0]
0
CLK1_7
ï¼»1]
0
CLK1_7
ï¼»0]
CLK1
Output State
Setting
0
CLK2_0
ï¼»1]
0
0
CLK2_0
ï¼»0]
0
0
CLK2_1
ï¼»1]
0
0
CLK2_1
ï¼»0]
0
0
CLK2_2
ï¼»1]
0
0
CLK2_2
ï¼»0]
0
0
CLK2_3
ï¼»1]
0
0
CLK2_3
ï¼»0]
0
CLK2
Output State
Setting
Sep -12
- 20 -
draft-E-06