AK8140A Datasheet, PDF (10/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
 Frequency setting procedure
When set the CLKn* output frequency to the same as the XIN input frequency (fin), set MUXn* to
‘XIN’ by the Register (address:0Ch). *n=1-4
-PLL1 Setting Procedure-
fin1
MDIV1 _{fcmp1 PFD/CP/LPF/}
NDIV1
VCO
fvco1
foutn
ODIVn
(INT+FRAC)
Figure.5 PLL1 Block Diagram
Output frequency from PLL1 is determined by PLL1 parameter: REFCLK Dividing value (MDIV1),
Fractional-N1 Dividing value (INT, FRAC), and OUTPUT Dividing value (ODIV1-4).
These parameters should be set as described below.
Step1. Deciding VCO1 target frequency.
This frequency (fvco1) is decided from CLKn Output frequency (foutn) and Output dividing value
(ODIVn, set by address: 0Dh~13h).Set fVCO1 frequency between 230MHz to 460MHz.
230MHz≦fVCO1≦460MHz (fVCO1=foutn×ODIVn)
Step2. Deciding Phase comparison frequency.
Set MDIV1 divider as this frequency (fcmp1) becomes between 6.75MHz to 13.5MHz.
6.75MHz≦fcmp1≦13.5MHz (fcmp1 = Fin1 / MDIV1)
Step3. Deciding Feedback dividing value.
This value is decided by VCO1 frequency (fvco1) and Phase comparison frequency (fcmp1).
7 bits integral part and 18 bits fractional part (signed 2’s complement) is necessary to be set.
Integral part (INT)
Fractional part (FRAC)
= round ( fvco1 / fcmp1 )
= round ( ( fvco1 / fcmp1 ) – INT ) x 2¹⁸ )
Sep -12
- 10 -
draft-E-06